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Step-GRAND: A Low Latency Universal Soft-input Decoder

Signal Processing 2023-07-28 v3 Hardware Architecture Information Theory math.IT

Abstract

GRAND features both soft-input and hard-input variants that are well suited to efficient hardware implementations that can be characterized with achievable average and worst-case decoding latency. This paper introduces step-GRAND, a soft-input variant of GRAND that, in addition to achieving appealing average decoding latency, also reduces the worst-case decoding latency of the corresponding hardware implementation. The hardware implementation results demonstrate that the proposed step-GRAND can decode CA-polar code (128,105+11)(128,105+11) with an average information throughput of 47.747.7 Gbps at the target FER of 107\leq10^{-7}. Furthermore, the proposed step-GRAND hardware is 10×10\times more area efficient than the previous soft-input ORBGRAND hardware implementation, and its worst-case latency is 16.8×\frac{1}{6.8}\times that of the previous ORBGRAND hardware.

Keywords

Cite

@article{arxiv.2307.07133,
  title  = {Step-GRAND: A Low Latency Universal Soft-input Decoder},
  author = {Syed Mohsin Abbas and Marwan Jalaleddine and Chi-Ying Tsui and Warren J. Gross},
  journal= {arXiv preprint arXiv:2307.07133},
  year   = {2023}
}

Comments

Submitted to 2023 IEEE Globecom Workshops

R2 v1 2026-06-28T11:30:04.863Z