Staggered Dslash Performance on Intel Xeon Phi Architecture

Ruizi Li; Steven Gottlieb

Staggered Dslash Performance on Intel Xeon Phi Architecture

High Energy Physics - Lattice 2014-11-11 v1 Computational Physics

Authors: Ruizi Li , Steven Gottlieb

Abstract

The conjugate gradient (CG) algorithm is among the most essential and time consuming parts of lattice calculations with staggered quarks. We test the performance of CG and dslash, the key step in the CG algorithm, on the Intel Xeon Phi, also known as the Many Integrated Core (MIC) architecture. We try different parallelization strategies using MPI, OpenMP, and the vector processing units (VPUs).

Keywords

graphics processing unit computing

Cite

@article{arxiv.1411.2087,
  title  = {Staggered Dslash Performance on Intel Xeon Phi Architecture},
  author = {Ruizi Li and Steven Gottlieb},
  journal= {arXiv preprint arXiv:1411.2087},
  year   = {2014}
}

Comments

7 Pages, 1 figure, contribution to the 32nd International Symposium on Lattice Field Theory (Lattice 2014), 23-28 June 2014, Columbia University, New York, NY, USA

Staggered Dslash Performance on Intel Xeon Phi Architecture

Abstract

Keywords

Cite

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