Spectrum Efficiency and Processing Latency Trade-offs in Panel-Based LIS
Abstract
The next generation wireless systems will face stringent new requirements, including ultra-low latency, high data rates and enhanced reliability. Large Intelligent Surfaces, is one proposed solution that has the potential to solve these high demands. The real-life deployment of such systems involves different design considerations with non-trivial trade-offs. This paper investigates the trade-off between spectral efficiency and processing latency, considering different antenna distribution schemes and detection algorithms. A latency model for the physical layer processing has been developed, using real FPGA and application-specific instruction processor (ASIP) hardware implementation results. Simulation results using an indoor environment show that distributing antennas throughout the scenario improves overall reliability, while the impact from this on latency is limited both when using zero-forcing (ZF) and Minimum Mean Square Error (MMSE) detection. Changing the detection algorithm to maximum-ratio combining (MRC) from ZF or MMSE, however, reduces the latency significantly, even if a larger number of antennas are needed to achieve a similar spectrum efficiency.
Keywords
Cite
@article{arxiv.2411.19147,
title = {Spectrum Efficiency and Processing Latency Trade-offs in Panel-Based LIS},
author = {Lina Tinnerberg and Dumitra Iancu and Ove Edfors and Liang Liu and Juan Vidal Alegría},
journal= {arXiv preprint arXiv:2411.19147},
year = {2025}
}
Comments
This work has been submitted to the IEEE for possible publication, copyright information may be affected upon publication