English

SPEC CPU: The Next Generation

Performance 2026-05-05 v1 Hardware Architecture

Abstract

The march toward developing relevant and robust CPU benchmarks continues with the introduction of SPEC CPU 2026, the next generation suite for measuring processor performance. This paper details the methodology behind its creation, showcasing a process centered on community collaboration and principled development. The suite is built upon a foundation of modern, open-source applications, selected and hardened through a process that emphasizes workload diversity, portability, and software longevity. A key contribution is Rolling-Round-Robin Rate, a novel and standardized approach to running heterogeneous, multiprogrammed workloads that addresses a long-standing gap in benchmarking practice. Additionally, the suite features an expanded set of multithreaded benchmarks and introduces workloads with distinct microarchitectural profiles, reflecting the demands of contemporary software. By detailing our principled approach to benchmark selection, adaptation, and validation, we demonstrate how the SPEC CPU 2026 suite sets the standard for performance evaluation in the next era of computer architecture research and development.

Keywords

Cite

@article{arxiv.2605.01575,
  title  = {SPEC CPU: The Next Generation},
  author = {Mahesh Madhav and Allen Lee and Andres Mejia and Branden Moore and Charan Soppadandi and Chris Cambly and Christoph Müllner and Daniel Bowers and David Reiner and Denis Bakhvalov and Di Zhao and Duane Voth and Feng Xue and Frédérique Silber-Chaussumier and James Bucek and James Southern and Jiangning Liu and Jim Himer and John Henning and Kevin Smith and Kristen Yang and Kunal Kashyap and Mason Guy and Mat Colgrove and Michael Berg and Prasad Battini and Prasad Joshi and Rohit Prasad and Shayantika Bhattacharya and Sriyash Caculo and Stefan Reimbold and Sundar Iyengar and Van Smith and Zarko Todorovski},
  journal= {arXiv preprint arXiv:2605.01575},
  year   = {2026}
}

Comments

24 pages, 6 figures, Presented at the 53rd Annual International Symposium on Computer Architecture (ISCA 2026), Raleigh, NC

R2 v1 2026-07-01T12:46:57.966Z