Sorting Network for Reversible Logic Synthesis
Hardware Architecture
2010-08-24 v1
Abstract
In this paper, we have introduced an algorithm to implement a sorting network for reversible logic synthesis based on swapping bit strings. The algorithm first constructs a network in terms of n*n Toffoli gates read from left to right. The number of gates in the circuit produced by our algorithm is then reduced by template matching and removing useless gates from the network. We have also compared the efficiency of the proposed method with the existing ones.
Keywords
Cite
@article{arxiv.1008.3694,
title = {Sorting Network for Reversible Logic Synthesis},
author = {Md. Saiful Islam and Md. Rafiqul Islam and Abdullah Al Mahmud and Muhammad Rezaul karim},
journal= {arXiv preprint arXiv:1008.3694},
year = {2010}
}
Comments
4 pages, 8 figures, 2 tables