Simple Linear-Size Additive Emulators
Abstract
Given an input graph , an additive emulator is a sparse weighted graph that preserves all distances in with small additive error. A recent line of inquiry has sought to determine the best additive error achievable in the sparsest setting, when has a linear number of edges. In particular, the work of [Kogan and Parter, ICALP 2023], following [Pettie, ICALP 2007], constructed linear size emulators with additive error. It is known that the worst-case additive error must be at least due to [Lu, Vassilevska Williams, Wein, and Xu, SODA 2022]. We present a simple linear-size emulator construction that achieves additive error . Our approach extends the path-buying framework developed by [Baswana, Kavitha, Mehlhorn, and Pettie, SODA 2005] and [Vassilevska Williams and Bodwin, SODA 2016] to the setting of sparse additive emulators.
Keywords
Cite
@article{arxiv.2310.17886,
title = {Simple Linear-Size Additive Emulators},
author = {Gary Hoppenworth},
journal= {arXiv preprint arXiv:2310.17886},
year = {2024}
}
Comments
SOSA24