English

Simple Linear-Size Additive Emulators

Data Structures and Algorithms 2024-01-09 v3

Abstract

Given an input graph G=(V,E)G = (V, E), an additive emulator H=(V,E,w)H = (V, E', w) is a sparse weighted graph that preserves all distances in GG with small additive error. A recent line of inquiry has sought to determine the best additive error achievable in the sparsest setting, when HH has a linear number of edges. In particular, the work of [Kogan and Parter, ICALP 2023], following [Pettie, ICALP 2007], constructed linear size emulators with +O(n0.222)+O(n^{0.222}) additive error. It is known that the worst-case additive error must be at least +Ω(n2/29)+\Omega(n^{2/29}) due to [Lu, Vassilevska Williams, Wein, and Xu, SODA 2022]. We present a simple linear-size emulator construction that achieves additive error +O(n0.191)+O(n^{0.191}). Our approach extends the path-buying framework developed by [Baswana, Kavitha, Mehlhorn, and Pettie, SODA 2005] and [Vassilevska Williams and Bodwin, SODA 2016] to the setting of sparse additive emulators.

Keywords

Cite

@article{arxiv.2310.17886,
  title  = {Simple Linear-Size Additive Emulators},
  author = {Gary Hoppenworth},
  journal= {arXiv preprint arXiv:2310.17886},
  year   = {2024}
}

Comments

SOSA24

R2 v1 2026-06-28T13:03:27.078Z