English

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators

Hardware Architecture 2024-06-17 v2 Artificial Intelligence

Abstract

To meet the growing need for computational power for DNNs, multiple specialized hardware architectures have been proposed. Each DNN layer should be mapped onto the hardware with the most efficient schedule, however, SotA schedulers struggle to consistently provide optimum schedules in a reasonable time across all DNN-HW combinations. This paper proposes SALSA, a fast dual-engine scheduler to generate optimal execution schedules for both even and uneven mapping. We introduce a new strategy, combining exhaustive search with simulated annealing to address the dynamic nature of the loop ordering design space size across layers. SALSA is extensively benchmarked against two SotA schedulers, LOMA and Timeloop on 5 different DNNs, on average SALSA finds schedules with 11.9% and 7.6% lower energy while speeding up the search by 1.7x and 24x compared to LOMA and Timeloop, respectively.

Keywords

Cite

@article{arxiv.2304.12931,
  title  = {SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators},
  author = {Victor J. B. Jung and Arne Symons and Linyan Mei and Marian Verhelst and Luca Benini},
  journal= {arXiv preprint arXiv:2304.12931},
  year   = {2024}
}

Comments

5 pages, 6 figures, open-source at https://github.com/ZigZag-Project/zigzag

R2 v1 2026-06-28T10:17:25.341Z