Field programmable gate arrays (FPGAs) can accelerate image processing by exploiting fine-grained parallelism opportunities in image operations. FPGA language designs are often subsets or extensions of existing languages, though these typically lack suitable hardware computation models so compiling them to FPGAs leads to inefficient designs. Moreover, these languages lack image processing domain specificity. Our solution is RIPL, an image processing domain specific language (DSL) for FPGAs. It has algorithmic skeletons to express image processing, and these are exploited to generate deep pipelines of highly concurrent and memory-efficient image processing components.
@article{arxiv.1508.07136,
title = {RIPL: An Efficient Image Processing DSL for FPGAs},
author = {Robert Stewart and Deepayan Bhowmik and Greg Michaelson and Andrew Wallace},
journal= {arXiv preprint arXiv:1508.07136},
year = {2016}
}
Comments
Presented at Second International Workshop on FPGAs for Software Programmers (FSP 2015) (arXiv:1508.06320)