ReveR: Software Simulator of Reversible Processor with Stack
Emerging Technologies
2011-06-01 v2 Hardware Architecture
Abstract
A software model of a reversible processor ReveR with the stack is discussed in this paper. An architecture, the minimal set of elementary reversible operations together with an implementation of the basic control flow structures and procedures calls using simple assembler language are described.
Cite
@article{arxiv.1104.0924,
title = {ReveR: Software Simulator of Reversible Processor with Stack},
author = {Alexander Yu. Vlasov},
journal= {arXiv preprint arXiv:1104.0924},
year = {2011}
}
Comments
LaTeX, 7 pages, no figures, 3 tables, v2: spelling and grammar corrected; project url http://friedmann.objectis.net/Members/vlasov/rever