Reconfigurable Hardware Implementation of the Successive Overrelaxation Method
Distributed, Parallel, and Cluster Computing
2019-05-17 v1 Hardware Architecture
Abstract
In this chapter, we study the feasibility of implementing SOR in reconfigurable hardware. We use Handel-C, a higher level design tool, to code our design, which is analyzed, synthesized, and placed and routed using the FPGAs proprietary software (DK Design Suite, Xilinx ISE 8.1i, and Quartus II 5.1). We target Virtex II Pro, Altera Stratix, and Spartan3L, which is embedded in the RC10 FPGA-based system from Celoxica. We report our timing results when targeting Virtex II Pro and compare them to software version results written in C++ and running on a general purpose processor (GPP).
Keywords
Cite
@article{arxiv.1905.06844,
title = {Reconfigurable Hardware Implementation of the Successive Overrelaxation Method},
author = {Safaa Kasbah and Ramzi Haraty and Issam Damaj},
journal= {arXiv preprint arXiv:1905.06844},
year = {2019}
}
Comments
15 pages, 5 figures, 4 tables. arXiv admin note: substantial text overlap with arXiv:1904.00629