As semiconductor scaling reaches the A16 / 2 nm node, the integration of co-packaged optics (CPO) via TSMC's Co-Packaged Optics Ultra Engine (COUPE) architecture introduces critical thermal-optical coupling challenges. Micro-ring resonators embedded in the Photonic Integrated Circuit (PIC) layer are exquisitely sensitive to temperature: a deviation of merely +-1.7 nm in resonant wavelength causes measurable Bit Error Rate (BER) degradation.
@article{arxiv.2605.18612,
title = {Predictive Software Scheduling as an Early-Warning Hint Layer for Optical Engine Thermal Drift in Heterogeneous SoIC Packaging},
author = {Chi Fei Chung},
journal= {arXiv preprint arXiv:2605.18612},
year = {2026}
}