Processing in memory (PIM) moves computation into memories with the goal of improving throughput and energy-efficiency compared to traditional von Neumann-based architectures. Most existing PIM architectures are either general-purpose but only support atomistic operations, or are specialized to accelerate a single task. We propose the Parallel Processor in Associative Content-addressable memory (PPAC), a novel in-memory accelerator that supports a range of matrix-vector-product (MVP)-like operations that find use in traditional and emerging applications. PPAC is, for example, able to accelerate low-precision neural networks, exact/approximate hash lookups, cryptography, and forward error correction. The fully-digital nature of PPAC enables its implementation with standard-cell-based CMOS, which facilitates automated design and portability among technology nodes. To demonstrate the efficacy of PPAC, we provide post-layout implementation results in 28nm CMOS for different array sizes. A comparison with recent digital and mixed-signal PIM accelerators reveals that PPAC is competitive in terms of throughput and energy-efficiency, while accelerating a wide range of applications and simplifying development.
@article{arxiv.1907.08641,
title = {PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations},
author = {Oscar Castañeda and Maria Bobbett and Alexandra Gallyas-Sanhueza and Christoph Studer},
journal= {arXiv preprint arXiv:1907.08641},
year = {2019}
}
Comments
Presented at the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2019