The PANDA experiment will not use any hardware trigger, i.e. all raw data are streaming in the data acquisition with a bandwidth of ~280 GB/s. The PANDA Online System is designed to perform data reduction by a factor of ~800 by reconstruction algorithms programmed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) on FPGAs (Field Programmable Gate Arrays).
Cite
@article{arxiv.0910.1682,
title = {Plans for PANDA Online Computing},
author = {Jens Soeren Lange and Dapeng Jin and Daniel Kirschner and Andreas Kopp and Wolfgang Kuehn and Johannes Lang and Lu Li and Ming Liu and ZhenAn Liu and David Muenchow and Tiago Perez and Johannes Roskoss and Qiang Wang and Hao Xu and Shuo Yang},
journal= {arXiv preprint arXiv:0910.1682},
year = {2011}
}
Comments
presented at Workshop on Fast Cerenkov Detectors, May 11-13, 2009, Giessen, Germany, 9 pages, 3 figures, accepted for publication in JINST