Static Random-Access Memory (SRAM) yield analysis is essential for semiconductor innovation, yet research progress faces a critical challenge: the large gap between simplified academic models and the complexities observed in practice. The lack of open, higher-fidelity benchmarks has hindered reproducibility and transferability, as promising academic techniques often fail to carry over to more realistic settings. We present OpenYield, an open-source ecosystem that aims to narrow this gap through three contributions: (i) An SRAM circuit generator that explicitly incorporates second-order effects (interconnect/line parasitics, inter-cell leakage coupling, and peripheral-circuit variations) that are commonly omitted in academic studies. (ii) A standardized evaluation platform with a simple interface and baseline yield-analysis implementations to enable fair comparisons and reproducible research on these higher-fidelity circuits. (iii) An optimization platform for transistor-level sizing under these models, supporting reproducible studies of robustness/efficiency trade-offs. OpenYield aims to foster more reproducible and transferable progress in SRAM-yield research. The framework is publicly available at https://github.com/ShenShan123/OpenYield
@article{arxiv.2508.04106,
title = {OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite},
author = {Shan Shen and Xingyang Li and Zhuohua Liu and Junhao Ma and Yikai Wang and Yiheng Wu and Yuquan Sun and Wei W. Xing},
journal= {arXiv preprint arXiv:2508.04106},
year = {2025}
}
Comments
The 43rd IEEE International Conference on Computer Design (ICCD2025), Best paper candidate from the EDA Track