On Fault Tolerance of Circuits with Intermediate Qutrit-assisted Gate Decomposition

The use of a few intermediate qutrits for efficient decomposition of 3-qubit unitary gates has been proposed, to obtain an exponential reduction in the depth of the decomposed circuit. An intermediate qutrit implies that a qubit is operated as a qutrit in a particular execution cycle. This method, primarily for the NISQ era, treats a qubit as a qutrit only for the duration when it requires access to the state $\ket{2}$ during the computation. In this article, we study the challenges of including fault-tolerance in such a decomposition. We first show that any qubit that requires access to the state $\ket{2}$ at any point in the circuit, must be encoded using a qutrit quantum error correcting code (QECC), thus resulting in a circuit with both qubits and qutrits at the outset. Since qutrits are noisier than qubits, the former is expected to require higher levels of concatenation to achieve a particular accuracy than that for qubit-only decomposition. Next, we derive analytically (i) the number of levels of concatenation required for qubit-qutrit and qubit-only decompositions as a function of the probability of error, and (ii) the criterion for which qubit-qutrit decomposition leads to a lower gate count than qubit-only decomposition. We present numerical results for these two types of decomposition and obtain the situation where qubit-qutrit decomposition excels for the example circuit of the quantum adder by considering different values for quantum hardware-noise and non-transversal implementation of the 2-controlled ternary CNOT gate.