English

Non Uniform On Chip Power Delivery Network Synthesis Methodology

Hardware Architecture 2017-11-08 v3

Abstract

In this paper, we proposed a non-uniform power delivery network (PDN) synthesis methodology. It first constructs initial PDN using uniform approach. Then preliminary power integrity analysis is performed to derive IR-safe candidate window. Congestion map is obtained based global route congestion estimation. A self-adaptive non-uniform PDN synthesis is then performed to globally and locally optimize PDN over selected regions. The PDN synthesis is congestion-driven and IR- guarded. Experimental results show significant timing important in trade-off small PDN length reduction with no EM/IR impact. We further explored potential power savings using our non-uniform PDN synthesis methodology.

Keywords

Cite

@article{arxiv.1711.00425,
  title  = {Non Uniform On Chip Power Delivery Network Synthesis Methodology},
  author = {Patrick Benediktsson and Jon A. Flandrin and Chen Zheng},
  journal= {arXiv preprint arXiv:1711.00425},
  year   = {2017}
}

Comments

6 pages, 5 figures, 3 tables

R2 v1 2026-06-22T22:33:14.339Z