English

Neat: Low-Complexity, Efficient On-Chip Cache Coherence

Hardware Architecture 2021-07-27 v2

Abstract

Cache coherence protocols such as MESI that use writer-initiated invalidation have high complexity and sometimes have poor performance and energy usage, especially under false sharing. Such protocols require numerous transient states, a shared directory, and support for core-to-core communication, while also suffering under false sharing. An alternative to MESI's writer-initiated invalidation is self-invalidation, which achieves lower complexity than MESI but adds high performance costs or relies on programmer annotations or specific data access patterns. This paper presents Neat, a low-complexity, efficient cache coherence protocol. Neat uses self-invalidation, thus avoiding MESI's transient states, directory, and core-to-core communication requirements. Neat uses novel mechanisms that effectively avoid many unnecessary self-invalidations. An evaluation shows that Neat is simple and has lower verification complexity than the MESI protocol. Neat not only outperforms state-of-the-art self-invalidation protocols, but its performance and energy consumption are comparable to MESI's, and it outperforms MESI under false sharing.

Keywords

Cite

@article{arxiv.2107.05453,
  title  = {Neat: Low-Complexity, Efficient On-Chip Cache Coherence},
  author = {Rui Zhang and Swarnendu Biswas and Vignesh Balaji and Michael D. Bond and Brandon Lucia},
  journal= {arXiv preprint arXiv:2107.05453},
  year   = {2021}
}
R2 v1 2026-06-24T04:06:27.203Z