Modern chip physical design relies heavily on Electronic Design Automation (EDA) tools, which often struggle to provide interpretable feedback or actionable guidance for improving routing congestion. In this work, we introduce a Multimodal Large Language Model Assistant (MLLMA) that bridges this gap by not only predicting congestion but also delivering human-interpretable design suggestions. Our method combines automated feature generation through MLLM-guided genetic prompting with an interpretable preference learning framework that models congestion-relevant tradeoffs across visual, tabular, and textual inputs. We compile these insights into a "Design Suggestion Deck" that surfaces the most influential layout features and proposes targeted optimizations. Experiments on the CircuitNet benchmark demonstrate that our approach outperforms existing models on both accuracy and explainability. Additionally, our design suggestion guidance case study and qualitative analyses confirm that the learned preferences align with real-world design principles and are actionable for engineers. This work highlights the potential of MLLMs as interactive assistants for interpretable and context-aware physical design optimization.
@article{arxiv.2510.15872,
title = {Multimodal Chip Physical Design Engineer Assistant},
author = {Yun-Da Tsai and Chang-Yu Chao and Liang-Yeh Shen and Tsung-Han Lin and Haoyu Yang and Mark Ho and Yi-Chen Lu and Wen-Hao Liu and Shou-De Lin and Haoxing Ren},
journal= {arXiv preprint arXiv:2510.15872},
year = {2025}
}