The balance metric is a simple approach to estimate the performance of bandwidth-limited loop kernels. However, applying the method to in-cache situations and modern multi-core architectures yields unsatisfactory results. This paper analyzes the in uence of cache hierarchy design on performance predictions for bandwidth-limited loop kernels on current mainstream processors. We present a diagnostic model with improved predictive power, correcting the limitations of the simple balance metric. The importance of code execution overhead even in bandwidth-bound situations is emphasized. Finally we analyze the impact of synchronization overhead on multi-threaded performance with a special emphasis on the in uence of cache topology.
@article{arxiv.0910.4865,
title = {Multi-core architectures: Complexities of performance prediction and the impact of cache topology},
author = {Jan Treibig and Georg Hager and Gerhard Wellein},
journal= {arXiv preprint arXiv:0910.4865},
year = {2009}
}