Multi-Channel FFT Architectures Designed via Folding and Interleaving
Signal Processing
2022-11-15 v1 Hardware Architecture
Abstract
Computing the FFT of a single channel is well understood in the literature. However, computing the FFT of multiple channels in a systematic manner has not been fully addressed. This paper presents a framework to design a family of multi-channel FFT architectures using {\em folding} and {\em interleaving}. Three distinct multi-channel FFT architectures are presented in this paper. These architectures differ in the input and output preprocessing steps and are based on different folding sets, i.e., different orders of execution.
Cite
@article{arxiv.2202.09623,
title = {Multi-Channel FFT Architectures Designed via Folding and Interleaving},
author = {Nanda K. Unnikrishnan and Keshab K. Parhi},
journal= {arXiv preprint arXiv:2202.09623},
year = {2022}
}
Comments
Proc. 2022 IEEE International Symposium on Circuits and Systems (ISCAS)