Modeling the EM Field Distribution within a Computer Chip Package

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. The study of the channel inside the chip is essential to minimize latency and power. However, this requires long and computationally-intensive simulations which take a lot of time. We propose and implement an analytical model of the EM propagation inside the package based on ray tracing. This model could compute the electric field intensity inside the chip reducing the computational time several orders of magnitude with an average mismatch of only 1.7 dB.