English

Modeling a Cache Coherence Protocol with the Guarded Action Language

Logic in Computer Science 2018-03-29 v1 Hardware Architecture

Abstract

We present a formal model built for verification of the hardware Tera-Scale ARchitecture (TSAR), focusing on its Distributed Hybrid Cache Coherence Protocol (DHCCP). This protocol is by nature asynchronous, concurrent and distributed, which makes classical validation of the design (e.g. through testing) difficult. We therefore applied formal methods to prove essential properties of the protocol, such as absence of deadlocks, eventual consensus, and fairness.

Keywords

Cite

@article{arxiv.1803.10323,
  title  = {Modeling a Cache Coherence Protocol with the Guarded Action Language},
  author = {Quentin L. Meunier and Yann Thierry-Mieg and Emmanuelle Encrenaz},
  journal= {arXiv preprint arXiv:1803.10323},
  year   = {2018}
}

Comments

In Proceedings MARS/VPT 2018, arXiv:1803.08668

R2 v1 2026-06-23T01:06:59.718Z