Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing

Mirko Brazzini; Giulio Filippeschi; Alessandro Catania; Sebastiano Strangio; Giuseppe Iannaccone

Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing

Hardware Architecture 2026-07-27 v1 Neural and Evolutionary Computing Applied Physics

Authors: Mirko Brazzini , Giulio Filippeschi , Alessandro Catania , Sebastiano Strangio , Giuseppe Iannaccone

Abstract

We show with experiments and system-level simulations that it is possible to successfully mitigate the impact of retention loss on inference accuracy degradation by using both circuit-level compensation techniques and batch normalization recalibration at the algorithmic level. Experiments are performed on a single-poly floating-gate (FG) analog non-volatile memory array for analog in-memory computing fabricated in a standard 65 nm CMOS. We use a model of retention-loss statistics calibrated with experiments to evaluate the system-level impact on neural network models such as VGG-10/CIFAR-10 and WideResNet-28-10/CIFAR-100. We show that, after 60 days since programming, combined mitigation techniques enable to recover the baseline inference accuracy within 2-4%

Keywords

analog in-memory computing retention loss floating-gate inference accuracy batch normalization circuit-level compensation

Cite

@article{arxiv.2607.25058,
  title  = {Mitigating the Impact of Retention Loss on Inference Accuracy in 65 nm Single-Poly Floating-Gate Analog In-Memory Computing},
  author = {Mirko Brazzini and Giulio Filippeschi and Alessandro Catania and Sebastiano Strangio and Giuseppe Iannaccone},
  journal= {arXiv preprint arXiv:2607.25058},
  year   = {2026}
}

Comments

4 pages, 3 figures