Mechanistic Insight into BEOL Thermal Transport via Optical Metrology and Multiphysics Simulation

As integrated circuits continue to scale down and adopt three-dimensional (3D) stacking, thermal management in the back-end-of-line (BEOL) has emerged as a critical design constraint. In this study, we present a combined experimental and simulation framework to quantitatively characterize and mechanistically understand thermal transport in BEOL multilayers. Using the Square-Pulsed Source (SPS) method, a time-resolved optical metrology technique, we measure cross-plane thermal resistance and areal heat capacity in semiconductor chips at nanometer resolution. Two fabricated chip samples, polished to the M4 and M6 interconnection layers, are analyzed to extract thermal properties of distinct multilayer stacks. Results show that thermal resistance follows a series model, while areal heat capacity scales linearly with metal content. To uncover the underlying physical mechanisms, we perform finite element simulations using COMSOL Multiphysics, examining the influence of via connectivity and dielectric thermal conductivity on effective cross-plane heat transport. The simulations reveal that dielectric materials, due to their large volume fraction, are the primary limiting factor in BEOL thermal conduction, while the via structure plays a secondary but significant role. This combined experimental-simulation approach provides mechanistic insight into heat transport in advanced IC architectures and offers practical guidance for optimizing thermal pathways in future high-performance 3D-stacked devices.