Majorization-based benchmark of the complexity of quantum processors

Here we investigate the use of the majorization-based indicator introduced in [R. O. Vallejos, F. de Melo, and G. G. Carlo, Phys. Rev. A 104, 012602 (2021)] as a way to benchmark the complexity within reach of quantum processors. By considering specific architectures and native gate sets of currently available technologies, we numerically simulate and characterize the operation of various quantum processors. We characterize their complexity for different native gate sets, qubit connectivity and increasing number of gates. We identify and assess quantum complexity by comparing the performance of each device against benchmark lines provided by randomized Clifford circuits and Haar-random pure states. In this way, we are able to specify, for each specific processor, the number of native quantum gates which are necessary, on average, for achieving those levels of complexity. Lastly, we study the performance of the majorization-based characterization in the presence of distinct types of noise. We find that the majorization-based benchmark holds as long as the circuits' output states have, on average, high purity ($\gtrsim 0.9$). In such cases, the indicator showed no significant differences from the noiseless case.