Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement.
@article{arxiv.2410.07989,
title = {Machine Learning-based feasibility estimation of digital blocks in BCD technology},
author = {Gabriele Faraone and Francesco Daghero and Eugenio Serianni and Dario Licastro and Nicola Di Carolo and Michelangelo Grosso and Giovanna Antonella Franchino and Daniele Jahier Pagliari},
journal= {arXiv preprint arXiv:2410.07989},
year = {2024}
}