Analog layout synthesis faces significant challenges due to its dependence on manual processes, considerable time requirements, and performance instability. Current Bayesian Optimization (BO)-based techniques for analog layout synthesis, despite their potential for automation, suffer from slow convergence and extensive data needs, limiting their practical application. This paper presents the \texttt{LLANA} framework, a novel approach that leverages Large Language Models (LLMs) to enhance BO by exploiting the few-shot learning abilities of LLMs for more efficient generation of analog design-dependent parameter constraints. Experimental results demonstrate that \texttt{LLANA} not only achieves performance comparable to state-of-the-art (SOTA) BO methods but also enables a more effective exploration of the analog circuit design space, thanks to LLM's superior contextual understanding and learning efficiency. The code is available at https://github.com/dekura/LLANA.
@article{arxiv.2406.05250,
title = {LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation},
author = {Guojin Chen and Keren Zhu and Seunggeun Kim and Hanqing Zhu and Yao Lai and Bei Yu and David Z. Pan},
journal= {arXiv preprint arXiv:2406.05250},
year = {2024}
}