English

Large Processor Chip Model

Hardware Architecture 2025-06-04 v1

Abstract

Computer System Architecture serves as a crucial bridge between software applications and the underlying hardware, encompassing components like compilers, CPUs, coprocessors, and RTL designs. Its development, from early mainframes to modern domain-specific architectures, has been driven by rising computational demands and advancements in semiconductor technology. However, traditional paradigms in computer system architecture design are confronting significant challenges, including a reliance on manual expertise, fragmented optimization across software and hardware layers, and high costs associated with exploring expansive design spaces. While automated methods leveraging optimization algorithms and machine learning have improved efficiency, they remain constrained by a single-stage focus, limited data availability, and a lack of comprehensive human domain knowledge. The emergence of large language models offers transformative opportunities for the design of computer system architecture. By leveraging the capabilities of LLMs in areas such as code generation, data analysis, and performance modeling, the traditional manual design process can be transitioned to a machine-based automated design approach. To harness this potential, we present the Large Processor Chip Model (LPCM), an LLM-driven framework aimed at achieving end-to-end automated computer architecture design. The LPCM is structured into three levels: Human-Centric; Agent-Orchestrated; and Model-Governed. This paper utilizes 3D Gaussian Splatting as a representative workload and employs the concept of software-hardware collaborative design to examine the implementation of the LPCM at Level 1, demonstrating the effectiveness of the proposed approach. Furthermore, this paper provides an in-depth discussion on the pathway to implementing Level 2 and Level 3 of the LPCM, along with an analysis of the existing challenges.

Keywords

Cite

@article{arxiv.2506.02929,
  title  = {Large Processor Chip Model},
  author = {Kaiyan Chang and Mingzhi Chen and Yunji Chen and Zhirong Chen and Dongrui Fan and Junfeng Gong and Nan Guo and Yinhe Han and Qinfen Hao and Shuo Hou and Xuan Huang and Pengwei Jin and Changxin Ke and Cangyuan Li and Guangli Li and Huawei Li and Kuan Li and Naipeng Li and Shengwen Liang and Cheng Liu and Hongwei Liu and Jiahua Liu and Junliang Lv and Jianan Mu and Jin Qin and Bin Sun and Chenxi Wang and Duo Wang and Mingjun Wang and Ying Wang and Chenggang Wu and Peiyang Wu and Teng Wu and Xiao Xiao and Mengyao Xie and Chenwei Xiong and Ruiyuan Xu and Mingyu Yan and Xiaochun Ye and Kuai Yu and Rui Zhang and Shuoming Zhang and Jiacheng Zhao},
  journal= {arXiv preprint arXiv:2506.02929},
  year   = {2025}
}
R2 v1 2026-07-01T02:57:04.147Z