Isadora is a methodology for creating information flow specifications of hardware designs. The methodology combines information flow tracking and specification mining to produce a set of information flow properties that are suitable for use during the security validation process, and which support a better understanding of the security posture of the design. Isadora is fully automated; the user provides only the design under consideration and a testbench and need not supply a threat model nor security specifications. We evaluate Isadora on a RISC-V processor plus two designs related to SoC access control. Isadora generates security properties that align with those suggested by the Common Weakness Enumerations (CWEs), and in the case of the SoC designs, align with the properties written manually by security experts.
Cite
@article{arxiv.2106.07449,
title = {Isadora: Automated Information Flow Property Generation for Hardware Designs},
author = {Calvin Deutschbein and Andres Meza and Francesco Restuccia and Ryan Kastner and Cynthia Sturton},
journal= {arXiv preprint arXiv:2106.07449},
year = {2021}
}