While the challenges and solutions for efficient execution of scalable vector ISAs on long-vector-length microarchitectures have been well established, not all of these solutions are suitable for short-vector-length implementations. This work proposes a novel microarchitecture for instruction sequencing in vector units with short architectural vector lengths. The proposed microarchitecture supports fine-granularity chaining, multi-issue out-of-order execution, zero dead-time, and run-ahead memory accesses with low area or complexity costs. We present the Saturn Vector Unit, a RTL implementation of a RVV vector unit. With our instruction scheduling mechanism, Saturn exhibits comparable or superior power, performance, and area characteristics compared to state-of-the-art long-vector and short-vector implementations.
Cite
@article{arxiv.2412.00997,
title = {Instruction Scheduling in the Saturn Vector Unit},
author = {Jerry Zhao and Daniel Grubb and Miles Rusch and Tianrui Wei and Kevin Anderson and Borivoje Nikolic and Krste Asanovic},
journal= {arXiv preprint arXiv:2412.00997},
year = {2024}
}