In this paper we use the Adapteva Epiphany manycore chip to demonstrate how the throughput and the latency of a baseband signal processing chain, typically found in LTE or WiFi, can be optimized by a combination of task- and data parallelization, and data pipelining. The parallelization and data pipelining are facilitated by the shared memory architecture of the Epiphany, and the fact that a processor on one core can write directly into the memory of any other core on the chip.
@article{arxiv.1512.05578,
title = {Improving Latency in a Signal Processing System on the Epiphany Architecture},
author = {Peter Brauer and Martin Lundqvist and Aare Mällo},
journal= {arXiv preprint arXiv:1512.05578},
year = {2015}
}
Comments
Draft paper submitted to and accepted by PDP 2016, 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing. Heraklion Crete, Greece, 17th-19th February 2016