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Hypervector Design for Efficient Hyperdimensional Computing on Edge Devices

Machine Learning 2021-03-12 v1 Hardware Architecture

Abstract

Hyperdimensional computing (HDC) has emerged as a new light-weight learning algorithm with smaller computation and energy requirements compared to conventional techniques. In HDC, data points are represented by high-dimensional vectors (hypervectors), which are mapped to high-dimensional space (hyperspace). Typically, a large hypervector dimension (1000\geq1000) is required to achieve accuracies comparable to conventional alternatives. However, unnecessarily large hypervectors increase hardware and energy costs, which can undermine their benefits. This paper presents a technique to minimize the hypervector dimension while maintaining the accuracy and improving the robustness of the classifier. To this end, we formulate the hypervector design as a multi-objective optimization problem for the first time in the literature. The proposed approach decreases the hypervector dimension by more than 32×32\times while maintaining or increasing the accuracy achieved by conventional HDC. Experiments on a commercial hardware platform show that the proposed approach achieves more than one order of magnitude reduction in model size, inference time, and energy consumption. We also demonstrate the trade-off between accuracy and robustness to noise and provide Pareto front solutions as a design parameter in our hypervector design.

Keywords

Cite

@article{arxiv.2103.06709,
  title  = {Hypervector Design for Efficient Hyperdimensional Computing on Edge Devices},
  author = {Toygun Basaklar and Yigit Tuncel and Shruti Yadav Narayana and Suat Gumussoy and Umit Y. Ogras},
  journal= {arXiv preprint arXiv:2103.06709},
  year   = {2021}
}

Comments

9 pages, 6 figures, accepted to tinyML 2021 Research Symposium