The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm.
@article{arxiv.cs/0605143,
title = {High-level synthesis under I/O Timing and Memory constraints},
author = {Philippe Coussy and Gwenolé Corre and Pierre Bomel and Eric Senn and Eric Martin},
journal= {arXiv preprint arXiv:cs/0605143},
year = {2016}
}