In this paper, we present Hexagon-MLIR,an open-source compilation stack that targets Qualcomm Hexagon Neural Processing Unit (NPU) and provides unified support for lowering Triton kernels and PyTorch models . Built using the MLIR framework, our compiler applies a structured sequence of passes to exploit NPU architectural features to accelerate AI workloads. It enables faster deployment of new Triton kernels (hand-written or subgraphs from PyTorch 2.0), for our target by providing automated compilation from kernel to binary. By ingesting Triton kernels, we generate mega-kernels that maximize data locality in the NPU's Tightly Coupled Memory (TCM), reducing the bandwidth bottlenecks inherent in library-based approaches. This initiative complements our commercial toolchains by providing developers with an open-source MLIR-based compilation stack that gives them a path to advance AI compilation capabilities through a more flexible approach. Hexagon-MLIR is a work-in-progress, and we are continuing to add many more optimizations and capabilities in this effort.
@article{arxiv.2602.19762,
title = {Hexagon-MLIR: An AI Compilation Stack For Qualcomm's Neural Processing Units (NPUs)},
author = {Mohammed Javed Absar and Muthu Baskaran and Abhikrant Sharma and Abhilash Bhandari and Ankit Aggarwal and Arun Rangasamy and Dibyendu Das and Fateme Hosseini and Franck Slama and Iulian Brumar and Jyotsna Verma and Krishnaprasad Bindumadhavan and Mitesh Kothari and Mohit Gupta and Ravishankar Kolachana and Richard Lethin and Samarth Narang and Sanjay Motilal Ladwa and Shalini Jain and Snigdha Suresh Dalvi and Tasmia Rahman and Venkat Rasagna Reddy Komatireddy and Vivek Vasudevbhai Pandya and Xiyue Shi and Zachary Zipper},
journal= {arXiv preprint arXiv:2602.19762},
year = {2026}
}