This letter introduces a framework for the automatic generation of hardware cores for Artificial Neural Network (ANN)-based chaotic oscillators. The framework trains the model to approximate a chaotic system, then performs design space exploration yielding potential hardware architectures for its implementation. The framework then generates the corresponding synthesizable High-Level Synthesis code and a validation testbench from a selected solution. The hardware design primarily targets FPGAs. The proposed framework offers a rapid hardware design process of candidate architectures superior to manually designed works in terms of hardware cost and throughput. The source code is available on GitHub.
@article{arxiv.2407.19165,
title = {HENNC: Hardware Engine for Artificial Neural Network-based Chaotic Oscillators},
author = {Mobin Vaziri and Shervin Vakili and M. Mehdi Rahimifar and J. M. Pierre Langlois},
journal= {arXiv preprint arXiv:2407.19165},
year = {2024}
}