English

Hardware Implementation of Neural Self-Interference Cancellation

Signal Processing 2020-05-08 v2 Hardware Architecture

Abstract

In-band full-duplex systems can transmit and receive information simultaneously on the same frequency band. However, due to the strong self-interference caused by the transmitter to its own receiver, the use of non-linear digital self-interference cancellation is essential. In this work, we describe a hardware architecture for a neural network-based non-linear self-interference (SI) canceller and we compare it with our own hardware implementation of a conventional polynomial based SI canceller. In particular, we present implementation results for a shallow and a deep neural network SI canceller as well as for a polynomial SI canceller. Our results show that the deep neural network canceller achieves a hardware efficiency of up to 312.8312.8 Msamples/s/mm2^2 and an energy efficiency of up to 0.90.9 nJ/sample, which is 2.1×2.1\times and 2×2\times better than the polynomial SI canceller, respectively. These results show that NN-based methods applied to communications are not only useful from a performance perspective, but can also be a very effective means to reduce the implementation complexity.

Keywords

Cite

@article{arxiv.2001.04543,
  title  = {Hardware Implementation of Neural Self-Interference Cancellation},
  author = {Yann Kurzo and Andreas Toftegaard Kristensen and Andreas Burg and Alexios Balatsoukas-Stimming},
  journal= {arXiv preprint arXiv:2001.04543},
  year   = {2020}
}

Comments

Accepted for publication in IEEE Journal on Emerging and Selected Topics in Circuits and Systems

R2 v1 2026-06-23T13:10:17.801Z