Hardware-Efficient Quantum Random Access Memory Design with a Native Gate Set on Superconducting Platforms
Abstract
Quantum Random Access Memory (QRAM) is a critical component for enabling data queries in superposition, which is the cornerstone of quantum algorithms. Among various QRAM architectures, the bucket-brigade model stands out due to its noise resilience. This paper presents a hardware-efficient native gate set {iSCZ, C-iSCZ} for implementing bucket-brigade QRAM on superconducting platforms. The experimental feasibility of the proposed gate set is demonstrated, showing high fidelity and reduced complexity. By leveraging the complementary control property in QRAM, our approach directly substitutes the conventional {SWAP, CSWAP} gates with the new gate set, eliminating decomposition overhead and significantly reducing circuit depth and gate count.
Cite
@article{arxiv.2306.10250,
title = {Hardware-Efficient Quantum Random Access Memory Design with a Native Gate Set on Superconducting Platforms},
author = {Yun-Jie Wang and Sheng Zhang and Tai-Ping Sun and Ze-An Zhao and Xiao-Fan Xu and Xi-Ning Zhuang and Huan-Yu Liu and Cheng Xue and Peng Duan and Yu-Chun Wu and Zhao-Yun Chen and Guo-Ping Guo},
journal= {arXiv preprint arXiv:2306.10250},
year = {2025}
}
Comments
19 pages, 15 figures