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Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs

Machine Learning 2026-04-10 v2 Artificial Intelligence Hardware Architecture

Abstract

Modern CNNs' high computational demands hinder edge deployment, as traditional ``hard'' sparsity (skipping mathematical zeros) loses effectiveness in deep layers or with smooth activations like Tanh. We propose a ``soft sparsity'' paradigm using a hardware efficient Most Significant Bit (MSB) proxy to skip negligible non-zero multiplications. Integrated as a custom RISC-V instruction and evaluated on LeNet-5 (MNIST), this method reduces ReLU MACs by 88.42% and Tanh MACs by 74.87% with zero accuracy loss--outperforming zero-skipping by 5x. By clock-gating inactive multipliers, we estimate power savings of 35.2% for ReLU and 29.96% for Tanh. While memory access makes power reduction sub-linear to operation savings, this approach significantly optimizes resource-constrained inference.

Keywords

Cite

@article{arxiv.2603.10100,
  title  = {Hardware Efficient Approximate Convolution with Tunable Error Tolerance for CNNs},
  author = {Vishal Shashidhar and Anupam Kumari and Roy P Paily},
  journal= {arXiv preprint arXiv:2603.10100},
  year   = {2026}
}

Comments

Submitted to IEEE GCON 2026

R2 v1 2026-07-01T11:13:40.928Z