In this paper, we present GradPIM, a processing-in-memory architecture which accelerates parameter updates of deep neural networks training. As one of processing-in-memory techniques that could be realized in the near future, we propose an incremental, simple architectural design that does not invade the existing memory protocol. Extending DDR4 SDRAM to utilize bank-group parallelism makes our operation designs in processing-in-memory (PIM) module efficient in terms of hardware cost and performance. Our experimental results show that the proposed architecture can improve the performance of DNN training and greatly reduce memory bandwidth requirement while posing only a minimal amount of overhead to the protocol and DRAM area.
@article{arxiv.2102.07511,
title = {GradPIM: A Practical Processing-in-DRAM Architecture for Gradient Descent},
author = {Heesu Kim and Hanmin Park and Taehyun Kim and Kwanheum Cho and Eojin Lee and Soojung Ryu and Hyuk-Jae Lee and Kiyoung Choi and Jinho Lee},
journal= {arXiv preprint arXiv:2102.07511},
year = {2021}
}