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GIC-DLC: Differentiable Logic Circuits for Hardware-Friendly Grayscale Image Compression

Computer Vision and Pattern Recognition 2026-01-21 v1

Abstract

Neural image codecs achieve higher compression ratios than traditional hand-crafted methods such as PNG or JPEG-XL, but often incur substantial computational overhead, limiting their deployment on energy-constrained devices such as smartphones, cameras, and drones. We propose Grayscale Image Compression with Differentiable Logic Circuits (GIC-DLC), a hardware-aware codec where we train lookup tables to combine the flexibility of neural networks with the efficiency of Boolean operations. Experiments on grayscale benchmark datasets show that GIC-DLC outperforms traditional codecs in compression efficiency while allowing substantial reductions in energy consumption and latency. These results demonstrate that learned compression can be hardware-friendly, offering a promising direction for low-power image compression on edge devices.

Keywords

Cite

@article{arxiv.2601.14130,
  title  = {GIC-DLC: Differentiable Logic Circuits for Hardware-Friendly Grayscale Image Compression},
  author = {Till Aczel and David F. Jenny and Simon Bührer and Andreas Plesner and Antonio Di Maio and Roger Wattenhofer},
  journal= {arXiv preprint arXiv:2601.14130},
  year   = {2026}
}
R2 v1 2026-07-01T09:12:43.531Z