G4LTL-ST: Automatic Generation of PLC Programs
Abstract
G4LTL-ST automatically synthesizes control code for industrial Programmable Logic Controls (PLC) from timed behavioral specifications of input-output signals. These specifications are expressed in a linear temporal logic (LTL) extended with non-linear arithmetic constraints and timing constraints on signals. G4LTL-ST generates code in IEC 61131-3-compatible Structured Text, which is compiled into executable code for a large number of industrial field-level devices. The synthesis algorithm of G4LTL-ST implements pseudo-Boolean abstraction of data constraints and the compilation of timing constraints into LTL, together with a counterstrategy-guided abstraction refinement synthesis loop. Since temporal logic specifications are notoriously difficult to use in practice, G4LTL-ST supports engineers in specifying realizable control problems by suggesting suitable restrictions on the behavior of the control environment from failed synthesis attempts.
Keywords
Cite
@article{arxiv.1405.2409,
title = {G4LTL-ST: Automatic Generation of PLC Programs},
author = {Chih-Hong Cheng and Chung-Hao Huang and Harald Ruess and Stefan Stattelmann},
journal= {arXiv preprint arXiv:1405.2409},
year = {2014}
}
Comments
This is the full version of the CAV'14 paper. Research concepts developed this paper are mainly from the technical report "Numerical LTL synthesis for cyber-physical systems", coauthored by Chih-Hong Cheng (ABB Research) and Edward A. Lee (UC Berkeley)