Brain-inspired computing and neuromorphic hardware are promising approaches that offer great potential to overcome limitations faced by current computing paradigms based on traditional von-Neumann architecture. In this regard, interest in developing memristor crossbar arrays has increased due to their ability to natively perform in-memory computing and fundamental synaptic operations required for neural network implementation. For optimal efficiency, crossbar-based circuits need to be compatible with fabrication processes and materials of industrial CMOS technologies. Herein, we report a complete CMOS-compatible fabrication process of TiO2-based passive memristor crossbars with 700 nm wide electrodes. We show successful bottom electrode fabrication by a damascene process, resulting in an optimised topography and a surface roughness as low as 1.1 nm. DC sweeps and voltage pulse programming yield statistical results related to synaptic-like multilevel switching. Both cycle-to-cycle and device-to-device variability are investigated. Analogue programming of the conductance using sequences of 200 ns voltage pulses suggest that the fabricated memories have a multilevel capacity of at least 3 bits due to the cycle-to-cycle reproducibility.
@article{arxiv.2106.11808,
title = {Fully CMOS-compatible passive TiO2-based memristor crossbars for in-memory computing},
author = {Abdelouadoud El Mesoudy and Gwénaëlle Lamri and Raphaël Dawant and Javier Arias-Zapata and Pierre Gliech and Yann Beilliard and Serge Ecoffey and Andreas Ruediger and Fabien Alibart and Dominique Drouin},
journal= {arXiv preprint arXiv:2106.11808},
year = {2021}
}