The High Level Trigger (HLT) of the ALICE experiment requires massive parallel computing. One of the main tasks of the HLT system is two-dimensional cluster finding on raw data of the Time Projection Chamber (TPC), which is the main data source of ALICE. To reduce the number of computing nodes needed in the HLT farm, FPGAs, which are an intrinsic part of the system, will be utilized for this task. VHDL code implementing the Fast Cluster Finder algorithm, has been written, a testbed for functional verification of the code has been developed, and the code has been synthesized
@article{arxiv.physics/0306017,
title = {FPGA Co-processor for the ALICE High Level Trigger},
author = {G. Grastveit and H. Helstrup and V. Lindenstruth and C. Loizides and D. Roehrich and B. Skaali and T. Steinbeck and R. Stock and H. Tilsner and K. Ullaland and A. Vestbo and T. Vik},
journal= {arXiv preprint arXiv:physics/0306017},
year = {2007}
}
Comments
Talk from the 2003 Computing in High Energy and Nuclear Physics (CHEP03), La Jolla, Ca, USA, March 2003, 5 pages, LaTeX, 8 eps figures. PSN THHT001, eConf C030324