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FPGA Based Implementation of Deep Neural Networks Using On-chip Memory Only

Hardware Architecture 2016-08-30 v2 Neural and Evolutionary Computing

Abstract

Deep neural networks (DNNs) demand a very large amount of computation and weight storage, and thus efficient implementation using special purpose hardware is highly desired. In this work, we have developed an FPGA based fixed-point DNN system using only on-chip memory not to access external DRAM. The execution time and energy consumption of the developed system is compared with a GPU based implementation. Since the capacity of memory in FPGA is limited, only 3-bit weights are used for this implementation, and training based fixed-point weight optimization is employed. The implementation using Xilinx XC7Z045 is tested for the MNIST handwritten digit recognition benchmark and a phoneme recognition task on TIMIT corpus. The obtained speed is about one quarter of a GPU based implementation and much better than that of a PC based one. The power consumption is less than 5 Watt at the full speed operation resulting in much higher efficiency compared to GPU based systems.

Keywords

Cite

@article{arxiv.1602.01616,
  title  = {FPGA Based Implementation of Deep Neural Networks Using On-chip Memory Only},
  author = {Jinhwan Park and Wonyong Sung},
  journal= {arXiv preprint arXiv:1602.01616},
  year   = {2016}
}

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Published in ICASSP 2016

R2 v1 2026-06-22T12:43:26.272Z