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Fixed Point Exploration For CV-QKD IR QC-MET-LDPC Toward Hardware Implementation

Hardware Architecture 2026-07-20 v1 Information Theory Quantum Physics

Abstract

High-speed LDPC decoding is a major bottleneck in CV-QKD and motivates hardware acceleration with fixed-point arithmetic. This work compares SPA, MSA, and NMS under a unified low-SNR fixed-point framework using common graph, matrix, and quantization settings. Multiple formats are evaluated through FER, and average iterations. The results show that performance depends strongly on the interaction between decoder rule and numerical precision. SPA achieved the best overall performance. For reduced-complexity decoders, Q16.8 was the lowest consistent precision, with NMS outperforming MSA. Practically, SPA with Q8.4 offered the best balance between reliability and hardware efficiency for large-scale implementations.

Cite

@article{arxiv.2607.17960,
  title  = {Fixed Point Exploration For CV-QKD IR QC-MET-LDPC Toward Hardware Implementation},
  author = {Guilherme Vergne de Oliveira and Mauro Queiroz Nooblath Neto and Micael Andrade Dias and Francisco Revson Fernandes Pereira and Francisco Marcos de Assis and Valéria Loureiro da Silva and Nelson Alves Ferreira},
  journal= {arXiv preprint arXiv:2607.17960},
  year   = {2026}
}

Comments

Accepted for publication in the XLIV Simpósio Brasileiro de Telecomunicações e Processamento de Sinais (SBrT 2026)