Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools
Hardware Architecture
2024-08-07 v1
Abstract
As Field Programmable Gate Arrays (FPGAs) computing capabilities continue to grow, also does the interest on building scientific accelerators around them. Tools like Xilinx's High-Level Synthesis (HLS) help to bridge the gap between traditional high-level languages such as C and C++, and low-level hardware description languages such as VHDL and Verilog. In this report, we study the implementation of a fluid dynamics application, the Finite-Time Lyapunov Exponent (FTLE) calculation, on FPGA using HLS. We provide speed and resource-consumption results for 2- and 3-dimensional cases.
Keywords
Cite
@article{arxiv.2408.02758,
title = {Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools},
author = {Manuel de Castro and Roberto R. Osorio and Francisco J. Andujar and Rocío Carratalá-Sáez and Yuri Torres and Diego R. Llanos},
journal= {arXiv preprint arXiv:2408.02758},
year = {2024}
}
Comments
8 pages, 2 tables