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Fault-Tolerant Deep Learning: A Hierarchical Perspective

Hardware Architecture 2022-04-06 v1 Artificial Intelligence Machine Learning

Abstract

With the rapid advancements of deep learning in the past decade, it can be foreseen that deep learning will be continuously deployed in more and more safety-critical applications such as autonomous driving and robotics. In this context, reliability turns out to be critical to the deployment of deep learning in these applications and gradually becomes a first-class citizen among the major design metrics like performance and energy efficiency. Nevertheless, the back-box deep learning models combined with the diverse underlying hardware faults make resilient deep learning extremely challenging. In this special session, we conduct a comprehensive survey of fault-tolerant deep learning design approaches with a hierarchical perspective and investigate these approaches from model layer, architecture layer, circuit layer, and cross layer respectively.

Keywords

Cite

@article{arxiv.2204.01942,
  title  = {Fault-Tolerant Deep Learning: A Hierarchical Perspective},
  author = {Cheng Liu and Zhen Gao and Siting Liu and Xuefei Ning and Huawei Li and Xiaowei Li},
  journal= {arXiv preprint arXiv:2204.01942},
  year   = {2022}
}

Comments

Special session submitted to VTS'22

R2 v1 2026-06-24T10:37:56.423Z