Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

Young-Taek Kim; Taehun Kim; Youngduk Kim; Chulho Shin; Eui-Young Chung; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

Hardware Architecture 2011-11-09 v1

Authors: Young-Taek Kim , Taehun Kim , Youngduk Kim , Chulho Shin , Eui-Young Chung , Kyu-Myung Choi , Jeong-Taek Kong , Soo-Kwan Eo

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Abstract

Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model shows 353 times faster than pin-accurate RTL model while maintaining 97% of accuracy on average. We also present the development procedure of TLM of a bus architecture.

Keywords

transaction level modeling AMBA2.0 AHB+ SoC performance analysis RTL model simulation speed cycle accuracy

Cite

@article{arxiv.0710.4808,
  title  = {Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture},
  author = {Young-Taek Kim and Taehun Kim and Youngduk Kim and Chulho Shin and Eui-Young Chung and Kyu-Myung Choi and Jeong-Taek Kong and Soo-Kwan Eo},
  journal= {arXiv preprint arXiv:0710.4808},
  year   = {2011}
}

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Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

Abstract

Keywords

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