Many convolutional neural network (CNN) accelerators face performance- and energy-efficiency challenges which are crucial for embedded implementations, due to high DRAM access latency and energy. Recently, some DRAM architectures have been proposed to exploit subarray-level parallelism for decreasing the access latency. Towards this, we present a design space exploration methodology to study the latency and energy of different mapping policies on different DRAM architectures, and identify the pareto-optimal design choices. The results show that the energy-efficient DRAM accesses can be achieved by a mapping policy that orderly prioritizes to maximize the row buffer hits, bank- and subarray-level parallelism.
@article{arxiv.2004.10341,
title = {DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks},
author = {Rachmad Vidya Wicaksana Putra and Muhammad Abdullah Hanif and Muhammad Shafique},
journal= {arXiv preprint arXiv:2004.10341},
year = {2023}
}
Comments
To appear at the 57th Design Automation Conference (DAC), July 2020, San Francisco, CA, USA