Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are applied on the gate-level netlist after logic synthesis, they have no semantic knowledge of the design function. Data-driven, machine-learning (ML) attacks can uncover the design flaws within gate-level locking. Recent proposals on register-transfer level (RTL) locking have access to semantic hardware information. We investigate the resilience of ASSURE, a state-of-the-art RTL locking method, against ML attacks. We used the lessons learned to derive two ML-resilient RTL locking schemes built to reinforce ASSURE locking. We developed ML-driven security metrics to evaluate the schemes against an RTL adaptation of the state-of-the-art, ML-based SnapShot attack.
@article{arxiv.2203.05399,
title = {Designing ML-Resilient Locking at Register-Transfer Level},
author = {Dominik Sisejkovic and Luca Collini and Benjamin Tan and Christian Pilato and Ramesh Karri and Rainer Leupers},
journal= {arXiv preprint arXiv:2203.05399},
year = {2022}
}
Comments
Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC '22)